Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Abstract This article presents Lock-V, a heterogeneous fault tolerance architecture that explores dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA Lock-VM by applying design diversity processor architectures at the instruction set (ISA)-level. features an Arm Cortex-A9 with RISC-V RV64GC, while includes Cortex-M3 along RV32IMA processor. solution field-programmable gate array (FPGA) technology deploy softcore versions of processors, dedicated accelerators for performing error detection triggering software rollback system used recovery. To test both fault-injection mechanism implemented cause bit-flips registers, common problem usually present heavy radiation environments.